CURTISS-WRIGHT 1
826448 VERSION 5 MARCH 2015 PROPRIETARY A-17
CHAMP-AV8 P1 (SRIO FABRIC) CONNECTOR PIN ASSIGNMENTS
The P1 connector is a 16 wafer VPX RT2 type connector shown in Figure A.9. The connector
provides access to the Serial RapidIO (SRIO) fabric interfaces of the CHAMP-AV8. The pinout
tables are presented in the order of the rows when looking from the backplane, (that is, i, h,
g, f, e, d, c, b, a).
Figure A.9: CHAMP-AV8 P1 SRIO Fabric Connector
See Table A.6 for connector pin assignments and Table A.7 on page A-18 for signal definitions.
Connector
Orientation:
i h g f e d c b a
VITA 46
P1 Wafer 1
to
P1 Wafer 16
Table A.6: P1 SRIO Fabric Connector Pin Assignments
Wafer
No.
Row G
Signal
Row F
Signal
Row E
Signal
Row D
Signal
Row C
Signal
Row B
Signal
Row A
Signal
1 BP_GDISCRETE1 GND PA_TX_N0 PA_TX_P0 GND PA_RX_N0 PA_RX_P0
2 GND PA_TX_N1 PA_TX_P1 GND PA_RX_N1 PA_RX_P1 GND
3 VBAT GND PA_TX_N2 PA_TX_P2 GND PA_RX_N2 PA_RX_P2
4 GND PA_TX_N3 PA_TX_P3 GND PA_RX_N3 PA_RX_P3 GND
5 SYS_CON_L GND PB_TX_N0 PB_TX_P0 GND PB_RX_N0 PB_RX_P0
6 GND PB_TX_N1 PB_TX_P1 GND PB_RX_N1 PB_RX_P1 GND
7 NC_RFU GND PB_TX_N2 PB_TX_P2 GND PB_RX_N2 PB_RX_P2
8 GND PB_TX_N3 PB_TX_P3 GND PB_RX_N3 PB_RX_P3 GND
9 CF_ALT_BOOT_L GND PC_TX_N0 PC_TX_P0 GND PC_RX_N0 PC_RX_P0
10 GND PC_TX_N1 PC_TX_P1 GND PC_RX_N1 PC_RX_P1 GND
11 CARD_FAIL_L GND PC_TX_N2 PC_TX_P2 GND PC_RX_N2 PC_RX_P2
12 GND PC_TX_N3 PC_TX_P3 GND PC_RX_N3 PC_RX_P3 GND
13 NC_IO_RSRV GND PD_TX_N0 PD_TX_P0 GND PD_RX_N0 PD_RX_P0
14 GND PD_TX_N1 PD_TX_P1 GND PD_RX_N1 PD_RX_P1 GND
15 MASKABLE
RESET_L
GND PD_TX_N2 PD_TX_P2 GND PD_RX_N2 PD_RX_P2
16 GND PD_TX_N3 PD_TX_P3 GND PD_RX_N3 PD_RX_P3 GND
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