CURTISS-WRIGHT PRODUCT OVERVIEW
826448 VERSION 5 MARCH 2015 PROPRIETARY 1-9
Figure 1.4: PCIe Switch Partitions
PCIe connections will typically auto-negotiate their link operating speed if different
generations of PCIe are mixed. For example, when mixing older hardware boards such as
the VPX6-185 or the CHAMP-AV6 with the CHAMP-AV8, the off-board PCIe links can
establish a common link speed in order to communicate. However, PCIe link speed and
other off-board PCIe signal parameters can be set to discrete values using BIOS settings.
See the BIOS User's Manual, Curtiss-Wright document 826450, for more information.
I/O Hub I/O Hub
VPX Backplane
Connector
DMI x4
DMI x4
XMC
Pn4
Intel Core i7 quad-core CPU A
J6
Node A
SDRAM
Control
SDRAM
Control
L3
PCIe
L1 / L2
Core
L1 / L2
Core
L1 / L2
Core
L1 / L2
Core
PCIe
PCIe
Node A
SDRAM
Control
SDRAM
Control
L3
PCIe
L1 / L2
Core
L1 / L2
Core
L1 / L2
Core
L1 / L2
Core
PCIe
PCIe
Factory
config
Intel Core i7 quad-core CPU B
PCIe Switch
x8 x8
NTB NTB
Partition 1
Partition 2
P2
EP[00:07]
P2
EP[08:15]
x0
2 x4
1 x8
x8/x0
2 x4
1 x8
2 x4
1 x8
Enumerated and
addressed by CPU B
Enumerated and
addressed by CPU A
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