CHAMP-AV8 (VPX6-462) HARDWARE USER’S MANUAL CURTISS-WRIGHT
1-16 PROPRIETARY 826448 VERSION 5 MARCH 2015
UTILITY FEATURES, SEMAPHORES, TIMERS
The CHAMP-AV8 features a number of utility features to facilitate multi-processor application
software. The board provides 16 hardware semaphore registers which are useful to coordinate
the sharing of hardware resources between multiple tasks. The hardware solution provides a
faster alternative to traditional software/memory techniques, and avoids the use of shared
memory to access the semaphores.
The CHAMP-AV8 provides six general purpose 32-bit timers. These may be configured for a
timeout value between 20ns and 85 seconds, with a resolution of 20ns. Each timer may be
configured to generate an interrupt to either processor. The current timer value may be read
at any time by software. Up to two timers may be reserved to support operating system
features.
AVIONICS STYLE WATCHDOG TIMER
The CHAMP-AV8 provides two watchdog timers for each processor. Each watchdog timer is a
pre-settable down-counter with a resolution of 1 µsec. Time-out periods from 0ms to 33.6
seconds can be programmed. Initialization software can select whether a watchdog exception
event causes a software interrupt, a processor reset, a card reset or a system reset. Once
enabled to cause a reset, the watchdog cannot be disabled. For development and maintenance
purposes, a backplane signal can be asserted to disable all watchdog interrupts. The watchdog
timer can be used in two ways:
• As a standard watchdog timer, a single time period is programmed which defines a max-
imum interval between writes to the watchdog register.
• For increased system integrity, the watchdog can be configured to operate in "Avionics"
mode, whereby a minimum interval between writes to the watchdog register is also
enforced. Writing to the watchdog register too soon or too late causes an exception
event.
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