CURTISS-WRIGHT PRODUCT OVERVIEW
826448 VERSION 5 MARCH 2015 PROPRIETARY 1-17
MULTI-BOARD SYNCHRONOUS CLOCK
The CHAMP-AV8 includes a special purpose counter which may be synchronized with
corresponding counters on other boards in the same system. This common time base allows
a developer to time-stamp messages and/or data buffers, with the knowledge that the local
time is maintained at the same value by all the boards in the system. The counter can be set
to roll-over to a pre-load value and interrupt on rollover. This feature is typically most valuable
for debugging and instrumenting multi-board applications code, which can present challenges
in coordinating the distribution of data items between processors.
SERIAL PORTS
The CHAMP-AV8 provides six serial ports. Two of these ports, one for each processor, are
EIA-422/485 electrical interfaces. The other four serial ports are user-configurable to operate
with either EIA-232 or EIA-422/485 electrical interfaces. The default configuration of the four
user-configurable ports is EIA-232. When configured to operate in EIA-422/485 mode, one
port utilizes the pins that are otherwise used by two EIA-232 ports. The following
configurations are possible:
• Four EIA-232, two from each processor node.
• Two EIA-232 from processor node A and one EIA-422/485 from processor node B.
• One EIA-422/485 from processor node A and two EIA-232 from processor node B.
• Two EIA-422/485, one from each processor node.
In both EIA-232 and EIA-422/485 configurations, the ports support transmit and receive
signals only. Internally the signals are routed through an FPGA which could optionally be
configured to provide a synchronous capability. Consult the factory for more information.
Two ports (one from each processor node, denoted as serial ports A0 and B0) are connected
to both the front panel connector (air-cooled cards) and to the backplane connector. Two
additional serial ports, one from each processor node and denoted as A1 and B1 are connected
to the backplane connector. The serial ports support asynchronous operation up to 115 Kbaud.
EIA-232/422/DDIO
Control
CHAMP-AV8 EIA-232/422 Scheme
On the CHAMP-AV8, processor node A has access to four UARTs, and node B has access to
three. Two UART ports on each node (A1/A0/B1/B0) are connected to on-board EIA-232/422
transceiver integrated circuits. The EIA-232/422 IC is a dual mode device which can be
configured either as (4 x EIA-232) or (2 x EIA-422) transceivers. Another UART in each node
(A2/B2) is connected to EIA-422 transceiver chips to form dedicated EIA-422 ports. The
remaining UART (A3) is currently unused.
The following combinations are supported by the Core Functions FPGA for serial port
multiplexing:
1. Two EIA-232 and one EIA-422 per node (total of six).
2. Two EIA-232 and one EIA-422 from Node A and two EIA-422 from Node B
3. Two EIA-422 from node A and two EIA-232, one EIA-422 from Node B
4. Two EIA-422 per node
When EIA-422 mode is selected for the dual-mode ports on either nodes A or B, UARTs A0/B0
are used to control the EIA-422 channels, and UARTs A1/B1 are disconnected. Figure 1.8
below shows a system-level implementation diagram for the UART and EIA-232/422
transceiver.
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