CHAMP-AV8 (VPX6-462) HARDWARE USER’S MANUAL CURTISS-WRIGHT
1-12 PROPRIETARY 826448 VERSION 5 MARCH 2015
CORE FUNCTIONS FPGA
The Core Functions FPGA (CF-FPGA) is illustrated in block diagram format below in Figure 1.6.
Figure 1.6: Core Functions FPGA Block Diagram
Clocks
Local Processor Block - 1
LPC-Bus I/F
Interrupts
Wdogs
X 2
WDogs
Timers
X 6
LED
Control
Local Processor Block – 2
(identical to LPB 1, except
no IPMI UART)
Internal Interrupts
PIB
BUS
I2O Block
Master
Slave
Project Specific Block (PSB)
SHMUART Block
Address
Decoding
I2C – Volt/
Temp Sensors
SPI - NVRAM
Reset CPLD/
Ctrl/Status
Address
Decoding
Address
Decodeing
I2O
X 4
Slave
Inbound FIFOs
8x64
4 sets of In/Outbound FIFO
Outbound FIFOs
8x64
Slave
BOOT-FLASH
SPI – Monitor
(to observe boot I/F)
PCH
SPI – I/F
Slave
Utility Block
Address
Decoding
MBSC
Misc. Ctrl &
Config. Status
Config
PROM I/F
DIO
Master
Clock Gen
LPC Clocks
MBSC Clock
Core Clock
Wdog/Timer Clock
PGOOD
monitoring
LPC_A
LPC_B
I2C – Pwr
Supply Ctrl
CLKs
UART
X 3 + 1 IPMI
XMC Status
Jumper Status
Semaphores
Boot Flash Select
Port 80
IPMI ctrl/status
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