CHAMP-AV8 (VPX6-462) HARDWARE USER’S MANUAL CURTISS-WRIGHT
1-18 PROPRIETARY 826448 VERSION 5 MARCH 2015
Figure 1.8: CHAMP-AV8 Serial Port Implementation
Access to the two dual-mode EIA-232/422 transceivers are multiplexed by the FPGA between
DIO[16] and UART A0 (also between DIO[17] and UART B0). This allows a DIO port to take
control of a EIA-422 differential pair, thus forming a DDIO (Differential DIO) port. Figure 1.9,
“CHAMP-AV8 Serial Port Detail,” on page 1-19 illustrates how the control registers are used to
control switching between the DIO registers, UART ports, and the EIA-232/422 dual-mode
transceiver.
NodeB
Intel®
PCH
Front Panel
Connector
NodeA
Intel®
PCH
LPC_ A
A0/A1
RS-232/422
Transceiver
ISL3333
1 RS 422 CH or
2 RS 232 CH
TXTX RXRX
B0/B1
RS-232/422
Transceiver
ISL3333
TX TXRX RX
Backplane Connector
CF- FPGA
SELSEL
REG
UART
A1
UART
A0
UART
B1
UART
B0
REG
LPC_ B
UART
A2
UART
B2
UART
A3
RS- 422
XCVR
RS- 422
XCVR
IPMI BMC
1 RS 422 CH or
2 RS 232 CH
TX
p/ n
RX
p/n
TX
p/n
RX
p/n
1 RS 422 CH
A0A1
B0
B1
LTC2855 LTC2855
1 RS 422 CH
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