CHAMP-AV8 (VPX6-462) HARDWARE USER’S MANUAL CURTISS-WRIGHT
1-6 PROPRIETARY 826448 VERSION 5 MARCH 2015
QUAD-CORE INTEL CORE I7 PROCESSORS
The CHAMP-AV8 incorporates two second or third generation Intel Core i7 quad-core
processors, which are a low power embedded implementation of micro-architecture code
name Sandy Bridge. A major advancement for DSP applications is the introduction of the
256-bit AVX floating-point instructions. The AVX vector unit is backwards compatible with SSE
instructions and doubles the peak floating-point performance over the previous generation. At
2.1GHz, each Core i7 processor provides a peak 135 GFlops. With two processors, the
CHAMP-AV8 provides 270 GFlops of performance.
Featuring a dual-channel, 1333 MHz DDR3 SDRAM interface, each CPU has a peak memory
bandwidth of 21GB/s. The 2nd and 3rd generation Core processors feature many
improvements in the cache subsystem designed to increase hit-rate and lower latency. Each
core contains first-level instruction and data caches (32 KB, 4-way) and a second level unified
cache (256 KB, 8-way).
A large third level cache (6MB 16-way) is shared between all processor cores. Intel’s
Hyper-Threading technology enables each core to execute two software threads concurrently.
Hyper-Threading results in a higher utilization rate of the CPU execution units and thus a
greater rate of instructions per unit of time.
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