CURTISS-WRIGHT 1
826448 VERSION 5 MARCH 2015 PROPRIETARY A-61
RTM P4 and P5
Discrete I/O (DIO)
Header Pin
Assignments
The CHAMP-AV8 Discrete I/O (DIO) signals are mapped to the RTM P4 and P5 headers as
shown below in Table A.42. DIO[0:7] are routed as single ended signals, while DIO[8:15] are
routed as differential I/O.
RTM P12
Geographical
Addressing
Header Pin
Assignments
On the CHAMP-AV8, the VITA 46 Geographical Addressing pins are routed to the CF-FPGA, so
that the CHAMP-AV8 can determine which slot it is in. These pins are also mapped to the P12
header on the RTM.
Table A.42: RTM Discrete I/O (P4, P5) Pin Assignments
DIO[0:7] Signals P4 Pin P5 Pin DIO[8:15] Signals
DIO0 22DIO8
DIO1 44DIO9
DIO2 66DIO10
DIO3 88DIO11
DIO4 10 10 DIO12
DIO5 12 12 DIO13
DIO6 14 14 DIO14
DIO7 16 16 DIO15
GND 1, 3, 5, 7, 9,
11, 15
1, 3, 5, 7, 9,
11, 15
GND
Table A.43: RTM Geographical Address (P12) Pin Assignments
Signal Name P12 Pin P12 Pin Signal Name
GA0_L 12GND
GA1_L 34GND
GA2_L 56GND
GA3_L 78GND
GA4_L 9 10 GND
GAP_L 11 12 GND
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