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Edge-Core AS7326-56X - Clock Tree

Edge-Core AS7326-56X
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EDGECORE NETWORKS CORPORATION 2018
13
BDX-DE
120pins connector
2x KR
PCIE3
X4
PCIE2
X1
BCM5720
SGMIIMIIM
USB-1
eUSB
Debug usb
PCIE2[0:1]
USB
USB
SATA
SATA mSATA
M.2 connector (option)
System SPI flash (Pri)
TPM
DDR4 SO-DIMM 0
DDR4 SO-DIMM 1
DDR-CH0
DDR-CH1
CPLD
PCA9617
DDR_I2C
SMB
EEPROM
0x56
LM75
0X4B
CPU XDP
PCH XDP
SVID
VCCIN=0X00
VCCSUSCUS=0X01
P1V2_VDDQ=0X02
SVID
25MHz
32.768Khz
RTCX1
RTCX2
XTAL25_IN
XTAL25_OUT
LAN_XTAL25_IN
LAN_XTAL25_OUT
25MHz
10GeB SPI flash
74AVCH4T245 TTL1T45
SPICLK
SPICS
SPIMOSI
SPIMISO
Level
shift
UART1
SUSCLK_GPIO62
Level
shift
UART0
LM75
SPI flash
CLOCKOUT_PCIE0
25MHz
IR3584MTRPBF
System SPI flash (Sec)
SPI
LPC
GPIO
LPC header
BMM
PCIE2_6
NCSI
PCA9548
0x77
I2C[0:1]
SML0_1
eth0
2.2.1. Clock Tree
The unit support has a Synchronous logic which consists of Network Interface Synchronizer
chip, Jitter attenuators and clock buffers. The key component is a Network Interface Synchronizer
chip.
The Network Interface Synchronizer chip selects a reference clock from one of two valid clock
sources generating a Stratum 3 compliant reference clock for the Broadcom Trident chip. This clock
is also used as a transmit reference clock for all external interface ports. This logic consists of a IDT
89307 Network Interface Synchronizer chip and Oven controlled crystal oscillator. This synchronizer
chip when properly configured will produce 25MHz and 156.25MHz clock which is frequency locked
to a selected port recovered clock.
The IDT 89307 is configured through an I2C interface, it reports major state information via a
number of status and control signals.
Figure 3 Switch board clock Tree

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