EDGECORE NETWORKS CORPORATION 2018
anywhere in 64-bit address range
4 KB anywhere in 64-bit address
range
Enable using standard PCI mechanism (D31:F6
TBAR/ TBARH)
4 KB anywhere in 64-bit address
range
Enable using standard PCI mechanism (D31:F6
TBARB/TBARBH)
16 Bytes anywhere in 64-bit
address range
Enable using standard PCI mechanism (D22:F 1:0)
4 KB anywhere in 4 GB range
Enable using standard PCI mechanism (D22:F3)
16 KB anywhere in 4 GB range
Root Complex Register Block (RCRB)
Enable using setting bit[0] of the Root Complex
Base Address register (D31:F0:offset F0h).
3.5. FLASH
There are four SPI flashs, 2 x 128Mb for BIOS, 1 x 32Mb for 10GBE controller +and 1 x 16Mb for
BCM5720.
The two 128Mb flash are for system boot BIOS, one is primary another one is backup.
There are two ways that can update the BIOS flash, one is via dediprog , the other is via BMC module. If
user want to update bios from BMC, the “BDX_SPI_MUX_SEL” would be pull low from high.
The 32Mb flash is for 10G controller setup and the 16Mb flash is for BCM5720 MAC setup.
The system boot flash SPI clock rate is 20MHz via the SPI memory mapped configuration register
SSFC[18:16] = “000” setting and the CPU GbE LAN SPI flash clock rate is 20MHz via the GBE LAN
memory mapped configuration register SSFC[18:16] = “000” setting.
Figure 16 FLASH Connection
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