Edge-Core AS7326-56X Programming Guide

EDGECORE NETWORKS CORPORATION 2018
176
5.12.8.31. Offset 0x46 Fan4 Vendor ID (Read Only)
Bit
Name
R/W
Reset Value
Description
7:3
Reserve
NA
NA
2:0
Fan4_Vendor ID
R
000
Fan Vendor control bit
Fan Vendor control bit
PIN[9, 10,11]
bit [9, 10,11]=100 -->AVC
bit [9, 10,11]=101 -->Sunon
bit [9, 10,11]=110 -->Nidec
5.12.8.32. Offset 0x47 Fan5 Vendor ID (Read Only)
Bit
Name
R/W
Reset Value
Description
7:3
Reserve
NA
NA
2:0
Fan5_Vendor ID
R
000
Fan Vendor control bit
Fan Vendor control bit
PIN[9, 10,11]
bit [9, 10,11]=100 -->AVC
bit [9, 10,11]=101 -->Sunon
bit [9, 10,11]=110 -->Nidec
5.12.8.33. Offset 0x48 Fan6 Vendor ID (Read Only)
Bit
Name
R/W
Reset Value
Description
7:3
Reserve
NA
NA
2:0
Fan6_Vendor ID
R
000
Fan Vendor control bit
Fan Vendor control bit
PIN[9, 10,11]
bit [9, 10,11]=100 -->AVC
bit [9, 10,11]=101 -->Sunon
bit [9, 10,11]=110 -->Nidec
5.12.9. CPLD Field upgrade information
The system support CPLD field upgrade function for main CPLD and Fan CPLD.
5.12.9.1. JTAG connection
 Main board and Fan board
Main board CPLD have three CPLD devices; CPLD1, CPLD2 and CPLD3. Fan board has one CPLD device.
The updater can update four CPLD devices in same time. CPU connects with CPLD’s Jtag interface via
CPU GPIO pin, and there has a JTAG chain in CPLD1, 2, 3 and Fan board CPLD.
5.12.9.2. Upgrade procedure
 Command for main board CPLD upgrade:
 ”TFTP_server_IP” : It is the IP address of TFTP server
 ”file_name.updater” : It is the file name of new CPLD image updater

Edge-Core AS7326-56X Specifications

General

Brand	Edge-Core
Model	AS7326-56X
Category	Switch
Language	English