3.1. Configurations of CPU
➢ 2 DDR channels support DDR4 ECC and non-ECC UDIMM, SODIMM, RDIMM
➢ Memory speed : DDR4 1600, 1867, 2133, 2400 MT/s
➢ PCI Express Lanes :
24Gen3, 1x16 and 1x8, 6 controllers x4 granularity (Uncore)
8 Gen2, 2x4, 8controlles x 1 granularity (Integrated PCH logic)
➢ Integrated 10GbE Controller contains two independent 10GbE MACs that support an
XGMII interface link to the either KX4 or KR PHY device interfaces.
KX4 PHY supports
XAUI for XGMII extension
10GBASE-KX4 for gigabit backplane applications.
2500BASE-KX for gigabit backplane applications.
1000BASE-KX for gigabit backplane applications.
KR PHY supports
10GBASE-KR for gigabit backplane application
1000BASE-KX for gigabit backplane application.
10GBASE SFP+ through a XFI compatible interface
10GBASE-T through a XFI compatible interface
➢ Integrated PCH logic
PCI Express Base specification, revision 2.0 support for up to eight ports with
transfers up to 5GT/s
ACPI power management logic support revision 4.0a
Enhanced DMA controller, interrupt controller, and timer function.
Integrated Serial ATA host controllers with independent DMA operation on up to six
ports.
xHCI USB controller provides support for up to 4 USB ports, of which four can be
configured as SuperSpeed USB 3.0 ports.
One legacy EHCI USB controller provides a USB debug port.
Integrated 10/100/1000 Gigabit Ethernet MAC witch system defense.
System Management Bus (SMBus) specification, version 2.0 with additional support
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