Edge-Core AS7326-56X - CPLD2 Pin-Out List

EDGECORE NETWORKS CORPORATION 2018
108
5.12.2.37. Offset 0x27 USB (Read & Write)
Bit
Name
R/W
Reset Value
Description
7:4
Reserved
NA
NA
3
USB_PWRON_N
R/W
1
1: USB enable (Default)
0: USB disable
2
USB1_VBUS
R
1
1: USB enable
0: USB disable
1
USB1_PWRFAULT
R/W
1
1: No interrupt (Default)
0: There is INTR to CPU
0
USB_PWRFLT_L
R
1
1: No interrupt
0: There is INTR from USB
5.12.2.38. Offset 0x28 MISC-1 (Read & Write)
Bit
Name
R/W
Reset Value
Description
7
Reserved
NA
NA
6
USB_UART_SUSPEND_L
R
0
0: Host USB port is in sleep mode or the USB cable is not
connected. (Default)
1: Host USB port and USB console port is active.
5
CPLD_USB_VBUS_DET
R
0
0: indicates that the RJ45 console is inserted. (Default)
1: indicates that the Micro USB console is inserted.
4
BU_SEL_2
R/W
0
1: Select JTAG link to FAN CPLD
0: Select JTAG link to CPLD3 (Default)
3
BU_SEL_1
R/W
0
1: Select JTAG link to MGMT PHY
0: Select JTAG link to CPLD2 (Default)
2
EE_WP
R/W
1
1: Enable EEPROM’s Write protection (Default)
0: Disable EEPROM’s Write protection
1
CPU_THERMALTRIP
NA
NA
Reserve
0
CPU_PROCHOT
NA
NA
Reserve
5.12.2.39. Offset 0x29 MISC-2 (Read & Write)
Bit
Name
R/W
Reset Value
Description
7
Reserved
NA
NA
6:5
PS[1:2]_AC-OK
NA
NA
Reserve
4:3
PS[1:2]_EEPROM_WP
NA
NA
Reserve
2
UCD9090_ALERT_L
NA
NA
Reserve
1
Fan_idle
NA
NA
Reserve
0
PCIE_WAKE_L
NA
NA
Reserve
5.12.3. CPLD2 pin-out list
Table 32 CPLD2 Pin-out List