Edge-Core AS7326-56X Programming Guide

EDGECORE NETWORKS CORPORATION 2018
74
Interrupt
Mgmt
PHY
MAC_INT_L
88
SYS_CPLD_INT_CPU
56
120Pins
BTB Connector
QSFP28 *8
CPLD23_INT_CPU
91
Reserved
FAN BOARD Connector
CPLD1
FAN_INT_L
LM75
LM75
LM75
x3
0x60
WAN PLL
IDT8V89307
IDT8V89307_INT_REQ
P49~P56_INT
LM75BD0~2_INT
CPLD2
CPLD2_INT
INT_MGMT_PHY_N
CPU Board
USB HUB
USB_PWRFLT_N
0x64
54
CPLD3_INT
PCIE_INTR_L
BCM56873
USB1_PWRFAULT
CPLD3
0x62
P1014
Shutdown_wake
SFP28 *18
SFP+_FLT_P33~P48
TX_FAULT_FX0~1
SFP+ *2
SFP28 *30
SFP+_FLT_P1~P32
5.8. JTAG
AS7326-56X had only done the JTAG download chain for three CPLD with JTAG interface, it
make the CPLD programing more quickly. The TCK and TMS pass to all devices by buffer. TDI and TDI
are connecting directly.
Figure 38 JTAG chain

Edge-Core AS7326-56X Specifications

General

Brand	Edge-Core
Model	AS7326-56X
Category	Switch
Language	English