Edge-Core AS7326-56X Programming Guide

EDGECORE NETWORKS CORPORATION 2018
20
for I2C devices
 Supports intel Virtualization Technology for Directed I/O (Intel VT-d)
 Supports intel Trusted Execution Technology (Intel TXT)
 Integrated clock controller
 Low Pin Count (LPC) interface
 Firmware Hub (FWH) interface support
 Serial Peripheral Interface (SPI) support
 JTAG Boundary scan support.
3.1.1. POR of CPU
The cores and uncore supports the following reset types. Note PWRGOOD_CPU is driven by the PCH.
Cold reset is the first time when the platform asserts PWRGOOD_CPU and asserts RESET_CPU_N to the
uncore. The platform has to wait for the Base Clock (BCLK) and the power to be stable before asserting
PWRGOOD_CPU. This results in reset of all the states in the processor, including the sticky state that is
preserved on the other resets. PLLs come up, I/O (DMI2,uncore PCI Express, and DDR) links undergo
initialization and calibration. Components in fixed and variable power planes are brought up. Ring,
router, SAD, and various lookup tables in the core/Cbo are initialized. Once the uncore initialization has
completed, then the power is enabled to the cores and cores are brought out of reset. BIOS is fetched
from the PCH.
Warm reset is typically a platform wide event and is indicated by assertion and deassertion of the
RESET_CPU_N signal on the socket while PWRGOOD_CPU remains asserted. This reset preserves the
error log state and machine check bank states for use by platform debug. The warm reset preserves
the error log state and machine check bank states for use by platform for post error event analysis. To
maintain the DDR memory attached to the processor self refresh and sticky registers remain valid
through out a warm reset, the "Reset_warn" message must complete by the processor. The
"Reset_warn" is a message that gets issued from the PCH to all sockets prior to warm reset. BIOS will
need to program the FlexRatioMSR/CSR in each socket and invoke the Warm Reset to the platform.
The reset flow is divided into the following 5 phases.
➢ Phase 0: Expectations from the platform (before assertion of PWRGOOD_CPU)
 Initially PWRGOOD_CPU signal is deasserted and RESET_CPU_N is asserted to the
socket. PWRGOOD_CPU cannot deassert until RESET_CPU_N is asserted.
 PWRGOOD_CPU must be asserted no sooner than 2 ms after the IVR Vccin supply
has fully ramped-up.
 Vccioin may be brought up before Vccin for IVR is brought up if not at the same
time. Vccioin is intended to source the PECI IO.
 The PWRGOOD_CPU and RESET_CPU_N signals have "clean" edges.
 The reference clock (BCLK) is stable.
 All external power rails have ramped as follows: Vccin, Vccioin, VCCD are up and
stable at their nominal values
 Assert PWRGOOD_CPU (RESET_CPU_N still asserted) only after 2 msec of Vccin,
Vccioin and VCCD at tolerance.
 After the power rails are up and stable for 2 msec and reference clocks are stable,
platform asserts PWRGOOD_CPU and continues to assert RESET_CPU_N signal to
the socket.
 PWRGOOD_CPU remains asserted as long as Vccin, Vccioin and VCCD remain stable.

Edge-Core AS7326-56X Specifications

General

Brand	Edge-Core
Model	AS7326-56X
Category	Switch
Language	English