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Edge-Core AS7326-56X Programming Guide

Edge-Core AS7326-56X
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EDGECORE NETWORKS CORPORATION 2018
38
DDR4
Sodimm-0
DDR0_CLK[0:1]
DDR0_MA[16:0]
DDR0_BA[1:0]
DDR0_BG[1:0]
DDR0_ACT_N
DDR0_PAR
DDR0_CS_N[1:0]
DDR0_CKE[1:0]
DDR0_ODT[1:0]
DDR0_DQ[63:0]
DDR0_DQS[8:0]
DDR0_ECC[7:0]
DDR0_ALERT_N
DDR4
Sodimm-1
DDR1_CLK[0:1]
DDR1_MA[16:0]
DDR1_BA[1:0]
DDR1_BG[1:0]
DDR1_ACT_N
DDR1_PAR
DDR1_CS_N[1:0]
DDR1_CKE[1:0]
DDR1_ODT[1:0]
DDR1_DQ[63:0]
DDR1_DQS[8:0]
DDR1_ECC[7:0]
DDR1_ALERT_N
CHANNEL-0 CHANNEL-1
DDR3_4_STRAP
BDXDE
VCCIOIN
3.7. PCIe
The CPU board has to provide the x4 PCIE Gen3 and x1 PCIE Gen2 to main board. The x4 PCIE GEN3 is
used to connect the NP8365 for control path, the PCIE GEN2 x1 is sued to communicate the OOB.
There are other PCIE GEN2 that connect to on board MAC BCM5720 and BMC module.
The PCIE interface connected to BCM5720 is PCIE GEN2 x2.
The PCIE interface connected to BMC module is PCIE GEN2 x1, which is used to active the graphic
inside the BMC chip to achieve the vKVM and vMedia function through IPMI when the BMC chip uses
AST2400.
Figure 18 PCIe Connection

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Edge-Core AS7326-56X Specifications

General IconGeneral
BrandEdge-Core
ModelAS7326-56X
CategorySwitch
LanguageEnglish

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