No power sequencing between Vccin and VCCD is required.
➢ Phase 1: PCU bring-up
Phase 1a: Activity Leading to PCU Start-up
Assertion of PWRGOOD_CPU (the trigger to move from the end Phase 0 to
thestart of Phase 1a).
Processor starts a timer (using BCLK) for determinism interval.
The PECI and SVID interfaces are held in reset until IVR asserts its power good
signal.
The PCU PLL is enabled.
Phase 1b: Pcode Controlled Preparing for Broad uncore Bring-Up
Starting at the sub-phase, all steps should be synchronous.
PCU micro controller comes out of reset to start reset pcode execution. This is
the planned "re-entry" point for Warm Reset processing.
Early reset pcode determines that it is at the start of Phase 1b.
Pcode brings the rest of the PCU hardware out of reset.
Pcode determines the boot config.
Pcode issues SVID command to ramp Vccin to 1.8V for cold reset.
Pcode reads and compares Vccin MBVR ICCMAX limit (reg 21h) vs its own
supported ICCMAX limit:
If VR's ICCMAX ≥ supported ICCMAX then bootup continues.
If VR's ICCMAX < supported ICCMAX then bootup halts and system shuts
down. MSR 411h IA32_MC4_STATUS logs Error code 0x1e -
MCA_VR_ICC_MAX_LESS_THAN_FUSED_ICC_MAX in field MSEC_FW.
Pcode sequences uncore non-boot IVRs to ramp up.
Pcode signals uncore power good to IIO, IMC.
Delivery of the uncore power good signals defines the transition from the end
of phase 1b to the beginning of phase 1c.
Phase 1c: PLL locking and IO Calibration
Pcode initiates thermal sensors.
Pcode locks PLLs in the following order: IIO, and IMC.
Pcode instructs the ring PLLs to start locking.
RESET_CPU_N signal is deasserted.
De-assertion of RESET_CPU_N signal will bring PCU out of reset and signifies
the transition from the end of Phase 1c to the beginning of Phase 2.
➢ Phase 2: Uncore initialization and core bring up
The starting assumptions are:
All IVRs except core IVRs have ramped-up and are stable.
All PLLs except core PLLs have locked.
Phase 2 is entered as a result of de-assertion of external pin RESET_CPU_N.
Boot mode related straps have been sampled and are available.
Some IO link calibration have started and may or may not have completed by
the start of this phase.
In this phase
PCU comes out of reset again and again determines the reset type.
Reset is deasserted to the ring units (HA, Cbo, IIO).
Reset is de-asserted to System Agents (IMC, IIO).
Pcode initializes the ring stops
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