Pcode performs boot mode processing based on straps. Set the advertised
firmware, IO, and Intel TXT agent bits appropriately.
Pcode services DMI2 handshake protocol. If DMI2 links are used in DMI2
mode, pcode checks if the links have trained to L0. If it's the legacy socket, and
if DMI2 links does not reach L0 within 3-4 ms, pcode executes error flow.
Pcode determines number of cores, slices and st/mt-threading for the core. In
this step pcode also takes into account number of BIOS-disabled cores. Pcode
determines whether BIST should be executed. BIST is executed if BIST Strap is
set or requested.
Pcode programs the logical ids and switches from physical to logical mode.
LLC reset and configuration.
If it's not service processor boot mode, pcode waits for links to get to
parameter exchange.
Pcode releases links to get to Normal operation (i.e. L0)
Pcode sets core Cstate to C1
➢ Phase 3: Reset execution (from core reset to fetch boot vector)
The starting assumptions are:
Before this phase starts, following information is provided to the core: APIC-ID,
whether it's the BSP, SMT enable/disable, reset type (cold, warm, C6 exit).
Uncore necessary to the get to the BIOS and Intel TXT Address space is fully
initialized.
In this phase:
Initialize core's internal structures, arrays, microarchitectural and architectural
state.
Execute MLC BIST if BIST enabled.
Initialize uncore.
Read LLC BIST results from the uncore and report it in the EAX register.
Report LLC and MLC BIST results.
The core and thread selected as package BSP fetches BIOS or goes to “Wait-
for-SIPI” state
The end assumption is there is at least one thread that was designated as
package BSP.
➢ Phase 4: BIOS execution
Figure 11 Power Sequencing Diagram G3 with RTC loss to S5
To Next Page
Loading...
Need help?
General