100 IBM z13s Technical Guide
3.4.14 Instruction set extensions
The processor supports many instructions to support functions:
Hexadecimal floating point instructions for various unnormalized multiply and multiply-add
instructions.
Immediate instructions, including various add, compare, OR, exclusive-OR, subtract, load,
and insert formats. Use of these instructions improves performance.
Load instructions for handling unsigned halfwords, such as those used for Unicode.
Cryptographic instructions, which are known as the MSA, offer the full complement of the
AES, SHA-1, SHA-2, and DES algorithms. They also include functions for random number
generation.
Extended Translate Facility-3 instructions, enhanced to conform with the current Unicode
4.0 standard.
Assist instructions that help eliminate hypervisor processor usage.
SIMD instructions, which allow the parallel processing of multiple elements in a single
instruction.
3.4.15 Transactional Execution
The Transactional Execution (TX) capability, which is known in the industry as hardware
transactional memory, runs a group of instructions atomically. That is, either all their results
are committed or no result is committed. The execution is optimistic. The instructions are run,
but previous state values are saved in a “transactional memory”. If the transaction succeeds,
the saved values are discarded. Otherwise, they are used to restore the original values.
The Transaction Execution Facility provides instructions, including declaring the beginning
and end of a transaction, and canceling the transaction. TX is expected to provide significant
performance benefits and scalability by avoiding most locks. This benefit is especially
important for heavily threaded applications, such as Java.
3.4.16 Runtime Instrumentation
Runtime Instrumentation (RI) is a hardware facility for managed run times, such as the Java
runtime environment (JRE). RI allows dynamic optimization of code generation as it is being
run. It requires fewer system resources than the current software-only profiling, and provides
information about hardware and program characteristics. It enhances JRE in making the
correct decision by providing real-time feedback.
3.5 Processor unit functions
This section describes the PU functions.
3.5.1 Overview
All PUs on a z13s server are physically identical. When the system is initialized, one
integrated firmware processor (IFP) is allocated from the pool of PUs that is available for the
whole system. The other PUs can be characterized to specific functions (CP, IFL, ICF, zIIP, or
SAP).
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