42 IBM z13s Technical Guide
Figure 2-7 shows the memory DIMM to PU SCM relationship and the various buses on the
nodes. Memory is connected to the SCMs through memory control units (MCUs). There is
one MCU per PU SCM that provide the interface to controller on memory DIMM. A memory
controller drives five DIMM slots.
Figure 2-7 CPC drawer logical structure
1
The buses are organized as follows:
The GX++ I/O bus slots provide connectivity for host channel adapters (HCAs). They are
fully buffered, and can sustain up to 6 GBps data transfer per bus direction. GXX++ I/O
slots provide support for InfiniBand and non-PCIe I/O features (FICON Express 8).
The PCIe I/O buses provide connectivity for PCIe fanouts and can sustain up to 18 GBps
data traffic per bus direction.
The X-bus provides interconnects between SC chip and PUs chips to each other, in the
same node.
The S-bus provides interconnects between SC chips in the same drawer.
The A-bus provides interconnects between SC chips in different drawers (through SMP
cables).
Processor support interfaces (PSIs) are used to communicate with FSP cards for system
control.
1
The drawing shows eight cores per PU chip. This is by design. The PU chip is a FRU shared with the z13. When
installed in a z13s server, each PU chip can have either six or seven active cores,
Inter-node
interface
S-BUS
Intra-node interface
X-BUS
Intra-node interface
X-BUS
PCIeMemory
8x cores
8x L1 cache
8x L2 cache
1x L3 cache
8x COP
MC, GX++, PCIe
GX++
Memory
8x cores
8x L1 cache
8x L2 cache
1x L3 cache
8x COP
MC, GX++, PCIe
GX++PSI
PCIe
480 MB +224 MB NIC
Directory L4 cache
SC
A-BUS
PCIe
8x cores
8x L1 cache
8x L2 cache
1x L3 cache
8x COP
MC, GX++, PCIe
GX++
Memory
8x cores
8x L1 cache
8x L2 cache
1x L3 cache
8x COP
MC, GX++, PCIe
GX++
PSI
PCIe
480 MB +224 MB NIC
Directory L4 cache
SC
A-BUS
Node 1
Node 0
CPC Drawer
To other
drawer
(SMP connector)
To other
drawer
(SMP connector)
Memory
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