440 IBM z13s Technical Guide
However, the path length that is associated with the operating system or subsystem might
vary based on a number of factors:
Competition with other tasks in the system for shared resources. As the total number of
tasks grows, more instructions are needed to manage the resources.
The n-way (number of logical processors) of the image or LPAR. As the number of logical
processors grows, more instructions are needed to manage resources that are serialized
by latches and locks.
12.3.2 Instruction complexity
The type of instructions and the sequence in which they are run interacts with the design of a
microprocessor to affect a performance component. This factor is defined as
instruction
complexity
. Many design alternatives affect this component:
Cycle time (GHz)
Instruction architecture
Pipeline
Superscalar
Out-of-order execution
Branch prediction
As workloads are moved between microprocessors with various designs, performance varies.
However, when on a processor, this component tends to be similar across all models of that
processor.
12.3.3 Memory hierarchy and memory nest
The memory hierarchy of a processor generally refers to the caches, data buses, and
memory arrays that stage the instructions and data that must be run on the microprocessor to
complete a transaction or job.
Many design choices affect this component:
Cache size
Latencies (sensitive to distance from the microprocessor)
Number of levels, the Modified, Exclusive, Shared, Invalid (MESI) protocol, controllers,
switches, the number and bandwidth of data buses, and others
Certain caches are
private to the microprocessor core, which means that only that
microprocessor core can access them. Other caches are shared by multiple microprocessor
cores. The term
memory nest for a z Systems processor refers to the shared caches and
memory along with the data buses that interconnect them.
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