92 IBM z13s Technical Guide
Here are some examples of SIMD instructions:
Integer byte to quadword add, sub, and compare
Integer byte to doubleword min, max, and average
Integer byte to word multiply
String find 8-bits, 16-bits, and 32-bits
String range compare
String find any equal
String load to block boundaries and load/store with length
For most operations, the condition code is not set. A summary condition code is used only for
a few instructions.
3.4.3 Out-of-order execution
z13s servers have an OOO core, much like the previous z114 and zBC12 systems. OOO
yields significant performance benefits for compute-intensive applications. It does so by
reordering instruction execution, allowing later (younger) instructions to be run ahead of a
stalled instruction, and reordering storage accesses and parallel storage accesses. OOO
maintains good performance growth for traditional applications. Out-of-order execution can
improve performance in the following ways:
Reordering instruction execution: Instructions stall in a pipeline because they are waiting
for results from a previous instruction or the execution resource that they require is busy. In
an in-order core, this stalled instruction stalls all later instructions in the code stream. In an
out-of-order core, later instructions are allowed to run ahead of the stalled instruction.
Reordering storage accesses: Instructions that access storage can stall because they are
waiting on results that are needed to compute the storage address. In an in-order core,
later instructions are stalled. In an out-of-order core, later storage-accessing instructions
that can compute their storage address are allowed to run.
Hiding storage access latency: Many instructions access data from storage. Storage
accesses can miss the L1 and require 7 - 50 more clock cycles to retrieve the storage
data. In an in-order core, later instructions in the code stream are stalled. In an
out-of-order core, later instructions that are not dependent on this storage data are
allowed to run.
The z13s processor has pipeline enhancements that benefit OOO execution. The z Systems
processor design has advanced micro-architectural innovations that provide these benefits:
Maximized instruction-level parallelism (ILP) for a better cycles per instruction (CPI)
design by reviewing every part of the z114 design
Maximized performance per watt
Enhanced instruction dispatch and grouping efficiency
Increased OOO resources (Global Completion Table entries, physical General Purpose
Register (GPR) entries, and physical FPR entries)
Improved completion rate
Reduced cache/TLB miss penalty
Improved execution of D-Cache store and reload, and new fixed-point divide
New oscillator card (OSC) (load-hit-store conflict) avoidance scheme
Enhanced branch prediction structure and sequential instruction fetching
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