522 IBM z13s Technical Guide
G.1 Design of native PCIe I/O adapter management
The native PCIe adapter is a new category of features introduced since zEC12. These
features are 10GbE Remote Direct Memory Access (RDMA) over Converged Ethernet
(RoCE) Express, zEnterprise Data Compression (zEDC) Express, and Flash Express. These
adapters are exclusively installed into a PCIe I/O drawer, together with the existing I/O
features and have a physical channel ID (PCHID) assigned according to its physical location.
For all the feature adapters installed in an I/O drawer, management functions in the form of
device drivers and diagnostic tools are always implemented to support virtualization of the
adapter, service, and maintenance.
Traditionally, these management functions are integrated on the adapter with specific
hardware design. For the newly introduced native PCIe adapters, these functions are moved
out of the adapter and are now handled by an IFP.
This section covers the following topics:
Native PCIe adapter
Integrated firmware processor
Resource groups
Management tasks
G.1.1 Native PCIe adapter
For traditional I/O adapters, such as the Open Systems Adapter (OSA) and Fibre Channel
connection (FICON) cards, the application-specific integrated circuit (ASIC) chip on the
adapter always downloads the device drivers and diagnostic tools from the Support Element
(SE) and runs the management functions on the adapter. In the new design, there is no ASIC
chip for management function on the native PCIe feature adapters.
For the RoCE and zEDC, device drivers and diagnostic tools are now running on the IFP and
use two RGs. Management functions, including virtualization, servicing and recovery,
diagnostics, failover, firmware updates against an adapter, and other functions are still
implemented.
G.1.2 Integrated firmware processor
The IFP is a processor unit (PU) exclusively used to manage native PCIe feature adapters
that are installed in the PCIe I/O drawer. On previous systems, this processor was not used
but known as a
reserved processor. It is allocated from the system PU pool and is not counted
in the PUs available for characterization.
If a native PCIe feature is installed in the system, the system allocates and initializes an IFP
during its power-on reset (POR) phase. Although the IFP is allocated to one of the physical
PUs, it is not visible to the users. In an error or failover scenario, PU sparing also happens for
an IFP, with the same rules as other PUs.
Note: Management of Flash Express feature is not covered in this section. All succeeding
topics apply to RoCE Express and zEDC Express only.
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