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IDEC FL1E-H12RCE - Page 337

IDEC FL1E-H12RCE
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Determining the cycle time
IDEC SmartRelay Manual 323
Explanation
The inverted marker block changes its output signal at each
program execution. Thus, one logic level (high or low) width
is exactly equivalent to the length of one cycle. Hence, a
period lasts 2 cycles.
The frequency trigger indicates the ratio of periods per 2
seconds, which res
ults in the r
atio of cycles per second.
Edge transition of the inverted marker at each
circuit program execution
Cycle time 1 period = 1 pulse = 2 cycles
Period
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