Appendix E: POST Code Diagnostic LED Decoder Intel® Server Board S2600CW Family TPS
Revision 2.4
Table 94. MRC Progress Codes
Code
subfunctions
Gather remaining SPD data
Program registers on the memory controller level
Evaluate RAS modes and save rank information
Program registers on the channel level
Perform the JEDEC defined initialization sequence
DDR Channel training done
Hardware memory test and init
Execute software memory init
Program memory map and interleaving
Program RAS configuration
Memory Initialization at the beginning of POST includes multiple functions, including:
discovery, channel training, validation that the DIMM population is acceptable and functional,
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