Intel® Intelligent Power Node Manager (NM) Support Overview
Intel® Server Board S2600CW Family TPS
96 Revision 2.4
foundation for automation of power management in the data center management stack. The
external interface specifies the protocols that must be supported in this version of NM.
6.3 ME System Management Bus (SMBus*) Interface
The ME uses the SMLink0 on the SSB in multi-master mode as a dedicated bus for
communication with the BMC using the IPMB protocol. The BMC FW considers this a
secondary IPMB bus and runs at 400 kHz.
The ME uses the SMLink1 on the SSB in multi-master mode bus for communication
with PMBus* devices in the power supplies for support of various NM-related features.
This bus is shared with the BMC, which polls these PMBus* power supplies for sensor
monitoring purposes (for example, power supply status, input power, and so on). This
bus runs at 100 KHz.
The Management Engine has access to the “Host SMBus*”.
6.4 PECI 3.0
The BMC owns the PECI bus for all Intel server implementations and acts as a proxy for the ME
when necessary.
6.5 NM “Discovery” OEM SDR
An NM “discovery” OEM SDR must be loaded into the BMC’s SDR repository if and only if the
NM feature is supported on that product. This OEM SDR is used by management software to
detect whether NM is supported and to understand how to communicate with it.
Since PMBus*-compliant power supplies are required in order to support NM, the system
should be probed when the SDRs are loaded into the BMC’s SDR repository in order to
determine whether the installed power supplies do in fact support PMBus*. If the installed
power supplies are not PMBus*-compliant, the NM “discovery” OEM SDR should not be
loaded.
Refer to the Intel
®
Intelligent Power Node Manager 2.0 External Architecture Specification using
IPMI for details of this interface.
6.6 SmaRT/CLST
The power supply optimization provided by SmaRT/CLST relies on a platform HW capability
as well as ME FW support. When a PMBus*-compliant power supply detects insufficient input
voltage, an over-current condition or an over-temperature condition, it will assert the
SMBAlert# signal on the power supply SMBus* (such as, the PMBus*). Through the use of
external gates, this results in a momentary assertion of the PROCHOT# and MEMHOT# signals
to the processors, thereby throttling the processors and memory. The ME FW also sees the
SMBAlert# assertion, queries the power supplies to determine the condition causing the
assertion, and applies an algorithm to either release or prolong the throttling, based on the
situation.
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