Intel S2600CW - Intel Secure Key; Intel os Guard; Trusted Platform Module (TPM); Integrated Memory Controller (IMC) and Memory Subsystem

Intel® Server Board S2600CW Functional Architecture Intel® Server Board S2600CW Family TPS
24 Revision 2.4
This PTAS-CUPS data can then be used in conjunction with the Intel® Server Platform Services
3.0 Intel® Node Manager power monitoring/controls and a remote management application
(such as the Intel® Data Center Manager [Intel® DCM]) to create a dynamic, automated,
closed-loop data center management and monitoring system.
3.2.11 Intel® Secure Key
It is the Intel® 64 and IA-32 Architectures instruction RDRAND and its underlying Digital
Random Number Generator (DRNG) hardware implementation. Among other things, the Digital
Random Number Generator (DRNG) using the RDRAND instruction is useful for generating
high-quality keys for cryptographic protocols. Please see more details from Intel® Digital
Random Number Generator Software Implementation Guide. It is intended to provide a
complete source of technical information on the RDRAND Instruction usage, including code
examples.
3.2.12 Intel® OS Guard
Intel® OS Guard protects the operating system (OS) from applications that have been
tampered with or hacked by preventing an attack from being executed from application
memory. Intel® OS Guard also protects the OS from malware by blocking application access to
critical OS vectors.
3.2.13 Trusted Platform Module (TPM)
Trusted Platform Module is bound to the platform and connected to the PCH via the LPC bus
or SPI bus. The TPM provides the hardware-based mechanism to store or “seal” keys and
other data to the platform. It also provides the hardware mechanism to report platform
attestations.
3.3 Integrated Memory Controller (IMC) and Memory Subsystem
This section describes the architecture that drives the memory subsystem, supported memory
types, memory population rules, and supported memory RAS features.
Figure 14. Memory Subsystem for Intel® Server Board S2600CW
Each installed processor includes an integrated memory controller (IMC). Each processor
supports 4 memory channels capable of supporting up to 2 DIMMs per channel. The
processor IMC supports the following: