Intel S2600CW - Publishing System Memory; RAS Features

Intel® Server Board S2600CW Family TPS Intel® Server Board S2600CW Functional Architecture
Revision 2.4
29
3.3.4 Publishing System Memory
There are a number of different situations in which the memory size and/or configuration are
displayed. Most of these displays differ in one way or another, so the same memory
configuration may appear to display differently, depending on when and where the display
occurs.
 The BIOS displays the “Total Memory” of the system during POST if Quiet Boot is
disabled in BIOS setup. This is the total size of memory discovered by the BIOS during
POST, and as well the sum of the individual sizes of installed DDR4 DIMMs in the
system.
 The BIOS displays the “Effective Memory” of the system in the BIOS Setup. The term
Effective Memory refers to the total size of all DDR4 DIMMs that are active (not
disabled) and not used as redundant units (see Note below).
 The BIOS provides the total memory of the system in the main page of BIOS setup.
This total is the same as the amount described by the first bullet above.
 If Quiet Boot is disabled, the BIOS displays the total system memory on the diagnostic
screen at the end of POST. This total is the same as the amount described by the first
bullet above.
 The BIOS provides the total amount of memory in the system by supporting the EFI
Boot Service function, GetMemoryMap().
 The BIOS provides the total amount of memory in the system by supporting the INT
15h, E820h function. For details, see the Advanced Configuration and Power Interface
Specification.
Note: Some server operating systems do not display the total physical memory installed. What
is displayed is the amount of physical memory minus the approximate memory space used by
system BIOS components. These BIOS components include but are not limited to:
 ACPI (may vary depending on the number of PCI devices detected in the system)
 ACPI NVS table
 Processor microcode
 Memory Mapped I/O (MMIO)
 Manageability Engine (ME)
 BIOS flash
3.3.5 RAS Features
 DRAM Single Device Data Correction (SDDC): SDDC provides error checking and
correction that protects against a single x4 DRAM device failure (hard-errors) as well as
multi-bit faults in any portion of a single DRAM device on a DIMM (require lockstep
mode for x8 DRAM device based DIMM).