Intel S7200AP - Page 98

Acronym Description
LOM LAN on Board
LRDIMM
Load Reduced DIMM memory modules have buffer registers for both address and data between the SDRAM
modules and the system's memory controller.
ME Management Engine
MM# Material Management number
MRC Memory Reference Code
MSB Most Significant Bit
MSID
CPU Icc Mismatch
MT/s MegaTransfers per second
NB
Northbound
NIC Network Interface Card
NVRAM Non-volatile RAM
OEM Original Equipment Manufacturer
OFU One-Boot Flash Update
OLTT Open Loop Thermal Throttling
OOB Out of Band
OS Operating System
PCH
Platform Controller Hub
PCI Peripheral Component Interconnect, or PCI Local Bus Standard – also called “Conventional PCI”
PCIe** PCI Express* -- an updated form of PCI offering better throughput and better error management
PEI Pre EFI Initialization. Component of Intel
®
Platform Innovation Framework for EFI architecture.
PEIM PEI Module
PERR Parity Error
PHM Processor Heatsink Module
POST Power On Self-Test – BIOS activity from the time on Power On until Operating System boot begins.
PSU Power Supply Unit
QPI Intel
®
QuickPath Interconnect
QR Quad Rank – memory DIMM organization, DRAMs organized in four ranks
RAID
Redundant Array of Inexpensive Disks – provides data security by spreading data over multiple disk drives.
RAID 0, RAID 1, RAID 10, and RAID 5 are different patterns of data on varying numbers of disks to provide
varying degrees of security and performance.
RAM Random Access Memory
RAS Reliability, Availability, and Serviceability
RC Raw Class
RDIMM
Registered DIMM (also called buffered) memory modules have an address buffer register between the SDRAM
modules and the system's memory controller.
ROM
Read-Only Memory
RT Runtime. Component of Intel
®
Platform Innovation Framework for EFI architecture
RTC Real Time Clock
SAD Source Address Decoder
SAS Serial Attached SCSI, a high speed serial data version of SCSI
SATA Serial ATA, a high speed serial data version of the disk ATA interface