The data generation consists of a Sample Memory which contains the sample data, a
Sequence Memory which contains the required information for sequencing like the
sequence structure or loop counter values and a Channel FPGA which combines
both into a sequence controlled sample stream. These parts cannot run at sample
clock rate and therefore multiple samples must be executed in parallel at a lower
clock speed. Depending on the selected direct mode, the Sync Clock, also called
Sequencer Clock is the sample clock divided by 64 (high speed mode) or by 48 (high
precision mode). When using the interpolated modes (refer to the chapter Digital
Up-Conversion), one Sync Clock cycle covers 24 delivered (not interpolated) IQ
sample pairs. Therefore, a sync clock cycle consists of “24*interpolation factor” DAC
samples.
The DAC converts the parallel sample stream to sample clock granularity. The analog
output of the DAC can either be used directly at the DIRECT OUT pin or can be
routed through two different available amplifier paths.
The clock generator can work on three clock sources: External Reference Clock (REF
CLK IN), the SAMPLE CLK IN or an internally generated clock. The two channels can
be delayed independently. The SYNC CLK OUT can be used to source the user’s
environment to provide synchronous signals at the TRIGGER IN and at the EVENT IN.
The Module FPGA is the common point of the instrument. The PCIe or USB 2.0 link is
connected to it as well as the Trigger and Event input and the port used for dynamic
sequencing. The whole chain from the Trigger/Event input to the Channel FPGA is
sourced with the Sync Clock. This allows providing an exact output delay from the
inputs to the DAC output for all cases where triggers and events are generated
based on the Sync Clock output and where the corresponding setup and hold time
conditions are met.
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