MEDIATEK Ralink MT7620 - Integrated 802.11 N Mac;Bbp and 2.4 Ghz Rf;Fem Router-On-A-Chip List of Tables; Default Chapter; List of Tables

PGMT7620_V.1.0_040503
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MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
List of Tables
TABLE 2-1 UART LITE INTERRUPT PRIORITIES ................................................................................................................. 75
TABLE 2-2 PDMA RX FIELD DESCRIPTIONS .................................................................................................................. 191
TABLE 2-3 RULE MASK ............................................................................................................................................. 249
TABLE 2-4 RATE CONTROL ........................................................................................................................................ 249
TABLE 2-5 RULE CONTROL ........................................................................................................................................ 249
TABLE 2-6 TRTCM METER TABLE ............................................................................................................................... 251
TABLE 2-7 ADDRESS TABLE WRITE DATA REGISTER: MAC ADDRESS ................................................................................. 277
TABLE 2-8 ADDRESS TABLE WRITE DATA REGISTER: DIP ENTRY ....................................................................................... 277
TABLE 2-9 ADDRESS TABLE WRITE DATA REGISTER: SIP ENTRY ....................................................................................... 277
TABLE 2-10 ADDRESS TABLE READ DATA REGISTER: MAC ENTRY .................................................................................... 279
TABLE 2-11 ADDRESS TABLE READ DATA REGISTER: DIP ENTRY....................................................................................... 280
TABLE 2-12 ADDRESS TABLE READ DATA REGISTER: SIP ENTRY ....................................................................................... 280
TABLE 2-13 VLAN AND ACL WRITE DATA-I REGISTER: VLAN ENTRY ............................................................................... 281
TABLE 2-14 VLAN AND ACL WRITE DATA-I REGISTER: ACL RULE TABLE .......................................................................... 282
TABLE 2-15 VLAN AND ACL WRITE DATA-I REGISTER: ACL RULE MASK .......................................................................... 282
TABLE 2-16 VLAN AND ACL WRITE DATA-I REGISTER: ACL RATE CONTROL ..................................................................... 282
TABLE 2-17 VLAN AND ACL WRITE DATA-I REGISTER: ACL RULE CONTROL ..................................................................... 282
TABLE 2-18 VLAN AND ACL WRITE DATA-I REGISTER: TRTCM METER TABLE ................................................................... 283
TABLE 2-19 VLAN AND ACL WRITE DATA-II REGISTER: VLAN ENTRY .............................................................................. 283
TABLE 2-20 VLAN AND ACL WRITE DATA-II REGISTER: ACL RULE TABLE ......................................................................... 283
TABLE 2-21 VLAN AND ACL WRITE DATA-II REGISTER: ACL RULE MASK ......................................................................... 283
TABLE 2-22 VLAN AND ACL WRITE DATA-II REGISTER: ACL RATE CONTROL .................................................................... 283
TABLE 2-23 VLAN AND ACL WRITE DATA-II REGISTER: ACL RULE CONTROL .................................................................... 283
TABLE 2-24 VLAN AND ACL WRITE DATA-II REGISTER: TRTCM METER TABLE .................................................................. 284
TABLE 2-25 DEBUG CONTROL REGISTER: DEBUG ID AND CONTROL .................................................................................. 289
TABLE 2-26 PCI/PCIE SCENERIO AND RELATIVE CONTROL REGISTER SETTINGS ..................................................................... 356
TABLE 2-27: 0X1398 TX_RATE_LUT_EN = 0 AND MULTI_MAC_ADDRESS = 0 ......................................................... 471
TABLE 2-28: 0X1398 TX_RATE_LUT_EN = 1 AND MULTI_MAC_ADDRESS = 0 ......................................................... 471
TABLE 2-29: 0X1398 TX_RATE_LUT_EN = 1 AND MULTI_MAC_ADDRESS = 1 ......................................................... 472
TABLE 3-1 IV/EIV FORMAT ...................................................................................................................................... 473
TABLE 3-2 WAPI_PN FORMAT ................................................................................................................................. 474
TABLE 3-3 WCID ATTRIBUTE ENTRY FORMAT .............................................................................................................. 475
TABLE 3-4 SHARED KEY MODE ENTRY FORMAT (1DW) ................................................................................................. 475
TABLE 3-5 PAIRWISE KEY TABLE (OFFSET: 0X4000) ....................................................................................................... 477
TABLE 3-6 IV/EIV TABLE (OFFSET: 0X6000) ................................................................................................................ 477
TABLE 3-7 WCID ATTRIBUTE TABLE (OFFSET: 0X6800) ................................................................................................. 477
TABLE 3-8 SHARED KEY TABLE (OFFSET: 0X6C00) ......................................................................................................... 478
TABLE 3-9 SHARED KEY MODE (OFFSET: 0X7000) ........................................................................................................ 478
TABLE 3-10 SHARED KEY MODE EXTENSION (FOR BSS_IDX=8 TO15) (OFFSET: 0X73F0) .................................................... 479
TABLE 3-11 SHARED KEY TABLE EXTENSION (FOR BSS_IDX=8 TO15) (OFFSET: 0X7400) .................................................... 480
TABLE 3-12 WAPI PN TABLE (EXTENSION OF IV/EIV TABLE) (OFFSET: 0X73F0) ............................................................... 480
TABLE 4-1 TX DESCRIPTOR FORMAT FIELD DESCRIPTIONS ............................................................................................... 483
TABLE 4-2 TXWI FRAME FORMAT.............................................................................................................................. 484
TABLE 4-3 TXWI FIELD DESCRIPTIONS ........................................................................................................................ 487
TABLE 4-4 RXWI FIELD DESCRIPTIONS ........................................................................................................................ 493
TABLE 4-5 BRIEF PHY RATE FORMAT AND DEFINITION .................................................................................................. 494
TABLE 4-6 MODULATION AND CODING SCHEME ........................................................................................................... 496