MEDIATEK Ralink MT7620 - Register Descriptions ( Base: 0 X 1000_0500)

PGMT7620_V.1.0_040503
Page 64 of 523
MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
2.6.4 Register Descriptions (base: 0x1000_0500)
46. RBR: Receive Buffer Register (offset: 0x0000)
Bits
Type
Name
Description
Initial Value
31:8
-
-
Reserved
-
7:0
RO
RXD
Receive Buffer Data
Data is transferred to this register from the
receive shift register after a full character is
received. If the contents of this register have
not been read before another character is
received, the OE bit in the LSR register is set,
indicating a received data buffer overrun.
0x0
47. TBR: Transmit Buffer Register (offset: 0x0004)
Bits
Type
Name
Description
Initial Value
31:8
-
-
Reserved
-
7:0
RO
TXD
Transmit Buffer Data
When a character is written to this register, it is
stored in the transmitter holding register. If the
transmitter register is empty, the character is
moved to the transmitter register, starting
transmission.
0x0
48. IER: Interrupt Enable Register (offset: 0x0008)
Bits
Type
Name
Description
Initial Value
31:4
-
-
Reserved
-
3
RW
EDSSI
Enable Modem Interrupt
Enables the following modem status interrupts.
 Data Carrier Detect (DCD)
 Ring Indicator (RI)
 Data Set Ready (DSR)
 Clear to Send (CTS)
 Delta Data Carrier Detect (DDCD)
 Trailing Edge Ring Indicator (TERI)
 Delta Data Set Ready (DDSR) to Send (DCTS)
0x0
2
RW
ELSI
Enable Receiver Line Status Interrupt
Enables the following receive line status
interrupts.
 Overrun Error (OE)
 Parity Error (PE)
 Framing Error (FE)
 Break Interrupt (BI)
0x0
1
RW
ETBEI
Enable Transmit Buffer Empty Interrupt
Enables the transmit buffer empty (THRE)
interrupt.
0x0