MEDIATEK Ralink MT7620 - Clock Plan

PGMT7620_V.1.0_040503
Page 14 of 523
MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
1.4 Clock Plan
BBP PLL
20/40 MHz
CPU PLL
(SSC)
600 MHz
EPHY
20/40 MHz
PCIe PHY (PLL)
USB PHY (TSMC)
12/48 MHz
PLL_PCIe CG
(w/ SSC)
20/40 Mhz
PCIe_CLK (EXT)
EPHY_CLK
125 MHz
PCIe_PHY_CLK
2.5 GHz
DRAM_CLK
/3
/4
/5
20/40 MHz
Xtal in
RF
100 MHz
250 MHz
GSW
480 MHz
/12
20/40 MHz
CLK_PERI
(Timer/Uart/I2C/I2S)
20/40 MHz
CPU_CLK
SYS_CLK
OCP_SYNC
/10
48 MHz
/4
12 MHz
PCM_480
20/40 MHz
PCM_240
/2
0
1
0
1
CPU_CLK_AUX0
CPU_CLK_AUX1
PCIe DRV
CLK_SDHC
PLL_CLK *
(1/M)
Figure 1-2 MT7620 Clock Diagram