MEDIATEK Ralink MT7620 - List of Registers

PGMT7620_V.1.0_040503
Page 18 of 523
MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
2.2.3 List of Registers
No.
Offset
Register Name
Description
Page
1
0x0000
CHIPID0_3
Chip ID ASCII Character 0-3
19
2
0x0004
CHIPID4_7
Chip ID ASCII Character 4-7
19
3
0x000C
REVID
Chip Revision Identification
19
4
0x0010
SYSCFG0
System Configuration Register 0
19
5
0x0014
SYSCFG1
System Configuration Register 1
20
6
0x0018
TESTSTAT
Firmware Test Status Register
22
7
0x001C
TESTSTAT2
Firmware Test Status Register 2
22
8
0x0020
Reserved
-
22
9
0x0024
Reserved
-
23
10
0x0028
Reserved
-
23
11
0x002C
CLKCFG0
Clock Configuration Register 0
23
12
0x0030
CLKCFG1
Clock Configuration Register 1
24
13
0x0034
RSTCTRL
Reset Control
25
14
0x0038
RSTSTAT
Reset Status
26
15
0x003C
CPU_SYS_CLKCFG
CPU and SYS Clock Control
27
16
0x0040
CLK_LUT_CFG
Clock Look Up Table Configuration
29
17
0x0044
CUR_CLK_STS
Current clock status
30
18
0x0048
BPLL_CFG0
BB PLL Configuration 0
31
19
0x004C
BPLL_CFG1
BB PLL Configuration 1
31
20
0x0054
CPLL_CFG0
CPU PLL Configuration 0
33
21
0x0058
CPLL_CFG1
CPU PLL Configuration 1
36
22
0x005C
USB_PHY_CFG
USB PHY control
36
23
0x0060
GPIOMODE
GPIO Purpose Select
36
24
0x0064
PCIPDMA_STAT
Control and Status of PDMA in PCIe Device
39
25
0x0088
PMU0_CFG
Power Management Unit 0 Configuration
39
26
0x008C
PMU1_CFG
Power Management Unit 1 Configuration
40
27
0x0098
PPLL_CFG0
PCIe PLL Configuration 0
41
28
0x009C
PPLL_CFG1
PCIe PLL Configuration 1
43
29
0x00A0
PPLL_DRV
PCIe Driver Configuration
44