MEDIATEK Ralink MT7620 - Table 2-25 Debug Control Register: D

PGMT7620_V.1.0_040503
Page 289 of 523
MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
Bits
Type
Name
Description
Initial Value
30:26
-
-
Reserved
0x0
25
RW
SIM_AGE
Age Timer Simulation Mode
Enables simulation mode on the age timer.
1'b0: Disable
1'b1: Only the first 8 entries are used and fast
age-out is performed on the age timer.
0x0
24
RW
PCNT_CHK
Page Count Check
Enables page link count check on Tx.
1'b0: Disabled
1'b1: Write page count info on PKT_MEM
0x0
23
RW
DBG_DIR
Debug Read/Write Direction
Debug read or write command.
DBG_CTRL and DBG_DATA are read from or
written to the corresponding latches.
0x0
22:16
RW
DBG_ID
Debug Identification
Debug ID for the different functions according
to the following table.
0x0
15:0
RW
DBG_CTRL
Debug Control
Debug mode control will be explained
according to the different Debug ID. DBG_CTRL
is used to control the debug data along with the
DBG_ID.
0x0
Table 2-25 Debug Control Register: Debug ID and Control
DBG_ID
Module
Bit
DBG_CTRL
Action
0x0
ARL_TBLSRCH
15
TRIG_ON
Enable Frame Trigger
Enable this bit to get the table data. This bit is auto-
cleared after frame capture is done.
0: Disable
1: Enable
14
-
Reserved
13:12
DATA_SEL
Output Data Selection
2’b00: MAC Control+Frame_Type
2’b01: VLAN Control+Frame_Type
2’b10: ACL Control+Frame_Type
2’b11: Reserved
11
DP Filter
Filter by Destination Port
10:6
Dest. Port
Indicates Destination Port
5
SP Filter
Filter by Source Port
4:0
Source Port
Source Port Indication
0x1
ARL_TBLSRCH
15
TRIG_ON
Enable Frame Trigger
Enable this bit to get the table data. This bit is auto-
cleared after frame capture is done.
0: Disable
1: Enable