MEDIATEK Ralink MT7620 - MIPS 24 K Processor

PGMT7620_V.1.0_040503
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MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
1. MIPS 24K Processor
1.1 Features
 8-stage pipeline
 32-bit address paths
 64-bit data paths to caches and external interfaces
 MIPS32-Compatible Instruction Set
 Multiply-Accumulate and Multiply-Subtract Instructions (MADD, MADDU, MSUB, MSUBU)
 Targeted Multiply Instruction (MUL)
 Zero/One Detect Instructions (CLZ, CLO)
 Wait instructions (WAIT)
 Conditional Move instructions (MOVZ, MOVN)
 Prefetch instructions (PREF)
 MIPS32 Enhanced Architecture (Release 2) Features
 Vectored interrupts and support for an external interrupt controller
 Programmable exception vector base
 Atomic interrupt enable/disable
 GPR shadow registers (one, three or seven additional shadows can be optionally added to minimize
latency for interrupt handlers)
 Bit field manipulation instructions
 MIPS32 Privileged Resource Architecture
 MIPS DSP ASE
 Fractional data types (Q15, Q31)
 Saturating arithmetic
 SIMD instructions operate on 2x16 b or 4x8 b simultaneously
 3 additional pairs of accumulator registers
 Programmable Memory Management Unit
 32 dual-entry JTLB with variable page sizes
 4-entry ITLB
 8-entry DTLB
 Optional simple Fixed Mapping Translation (FMT) mechanism
 MIPS16e™ Code Compression
 16-bit encodings of 32-bit instructions to improve code density
 Special PC-relative instructions for efficient loading of addresses and constants
 SAVE & RESTORE macro instructions for setting up and tearing down stack frames within subroutines
 Improved support for handling 8 and 16-bit datatypes
 Programmable L1 Cache Sizes
 Instruction cache size: 32 KB
 Data cache size: 16 KB
 4-Way Set Associative
 Up to 8 outstanding load misses
 Write-back and write-through support
 32-byte cache line size