MEDIATEK Ralink MT7620 - Register Descriptions ( Base: 0 X 1000_0 A00)

PGMT7620_V.1.0_040503
Page 155 of 523
MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
2.14.5 Register Descriptions (base: 0x1000_0A00)
191. I2S_CFG: I
2
S Tx/Rx Configuration Register (offset: 0x0000)
Bits
Type
Name
Description
Initial Value
31
RW
I2S_EN
I
2
S Enable
Enables I
2
S. When disabled, all I
2
S control
registers are cleared to their initial values.
0: Disable
1: Enable
0x0
30
RW
DMA_EN
DMA Enable
Enables DMA access.
0: Disable
1: Enable
0x0
29
-
-
Reserved
0x0
28
RW
BYTE_SWAP
Swaps the order of data bytes in each 16-bit
channel.
0: No data swap
1: Data byte swap
0x0
27:25
-
-
Reserved
0x0
24
RW
TX_EN
Transmitter on/off control
0: Disable
1: Enable
0x0
23:21
-
-
Reserved
0x0
20
RW
RX_EN
Receiver on/off control
0: Disable
1: Enable
0x0
19:17
-
-
Reserved
0x0
16
RW
SLAVE_MODE
Sets master or slave mode.
0: Master: using internal clock
1: Slave: using external clock
0x1
15
-
-
Reserved
0x0
14:12
RW
RX_FF_THRES
Rx FIFO Threshold
When the threshold is reached, the host/DMA
is notified to fill FIFO. 2<RX_FF_THRES<6
(unit: word)
0x4
11:7
-
-
Reserved
0x0
6:4
RW
TX_FF_THRES
Tx FIFO Threshold
When the threshold is reached, the host/DMA
is notified to fill FIFO.
2<TX_FF_THRES<6
(unit: word)
0x4
3:0
-
-
Reserved
0x0