MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
2.4.4 Register Descriptions (base: 0x1000_0200)
37. IRQ0STAT: Interrupt Type 0 Status after Enable Mask (offset: 0x0000)
USB device interrupt status after mask
USB host interrupt status after mask
Ethernet Switch interrupt status after mask
SDHC interrupt after mask
UARTLITE interrupt status after mask
SPI interrupt status after mask
I2S interrupt status after mask
MIPS performance counter interrupt status
after mask
DMA interrupt status after mask
PIO interrupt status after mask
UART interrupt status after mask
PCM interrupt status after mask
Illegal access interrupt status after mask
Watchdog timer interrupt status after mask
Timer 0 interrupt status after mask
System control interrupt status after mask
NOTE: These bits are set if the corresponding interrupt is asserted from the source and with the following two
conditions.
1. The interrupt is not masked (the bit is not set in the INTDIS register)
2. The interrupt type is set to INT0 (in the INTTYPE register).
NOTE: Writing to these bits is ignored and each bit cannot be simultaneously active in both the IRQ0STAT and
IRQ1STAT registers.
38. IRQ1STAT: Interrupt Type 1 Status after Enable Mask (offset: 0x0004)
USB device interrupt status after mask
USB host interrupt status after mask
Ethernet Switch interrupt status after mask
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