MEDIATEK Ralink MT7620 - Register Descriptions ( Base: 0 X 1000_0600)

PGMT7620_V.1.0_040503
Page 84 of 523
MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
2.8.4 Register Descriptions (base: 0x1000_0600)
71. GPIO23_00_INT: PIO Pin Interrupt Status (offset: 0x0000)
Bits
Type
Name
Description
Initial Value
31:24
-
-
Reserved
-
23:0
RC
PIOINT
PIO Pin Interrupt
A PIOINT bit is set when its corresponding PIO
pin changes value and the edge for that pin is
enabled via the PIORMASK or PIOFMASK
register. The pin must be set as an input in the
PIODIR register to generate an interrupt.
Read
0: No change detected.
1: Change detected.
Write
All bits are cleared by writing 1 to either this
register or the PIOEDGE register.
NOTE: Changes to the PIO pins can only be
detected when the clock is running.
0x0
72. GPIO23_00_EDGE: PIO Pin Edge Status (offset: 0x0004)
Bits
Type
Name
Description
Initial Value
31:24
-
-
Reserved
-
23:0
RC
PIOEDGE
The PIOEDGE bits have different meanings
depending on whether the interrupt for that pin
is enabled via the PIORMASK or PIOFMASK
register.
Read
If the PIO PIN Interrupt for this PIO pin is
asserted, the corresponding PIOEDGE bit
indicates whether a falling or rising edge
triggered the interrupt.
0: Interrupt triggered by falling edge.
1: Interrupt triggered by rising edge.
If the interrupt is masked (disabled), the
PIOEDGE bit is set on either a rising or falling
edge and remains set until cleared by firmware.
Bits corresponding to pins that are not set as
inputs will never be set.
Write
All bits are cleared by writing 1 to either this
register or the PIOINT register.
NOTE: Changes to the PIO pins can only be
detected when the clock is running.
0x0