MEDIATEK Ralink MT7620 - Uart Lite Interrupt Priorities

PGMT7620_V.1.0_040503
Page 75 of 523
MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
62. IIR: Interrupt Identification Register (offset: 0x000C)
Bits
Type
Name
Description
Initial Value
31:8
-
-
Reserved
0x0
7:6
RO
FIFOENA
FIFOs Enabled
These bits reflect the FIFO enable bit setting in
the FIFO Control Register.
00: FIFO enable bit is cleared.
11: FIFO enable bit is set.
0x0
5:4
-
-
Reserved
0x0
3:1
RO
INTID
Interrupt Identifier
These bits provide a snapshot of the interrupt
type, and may be used as the offset into an
interrupt vector table.
See NOTE below.
0x0
0
RO
INTPEND
Interrupt Pending
0: An interrupt bit is set and is not masked.
1: No interrupts are pending.
0x1
NOTE:
The interrupt encoding is given below.
Table 2-1 UART Lite Interrupt Priorities
ID
Priority
Type
Source
7
Undefined
6
Undefined
5
Undefined
4
Undefined
3
1 (highest)
Receiver Line Status
OE, PE, FE, BI
2
2
Receiver Buffer Full
DR
1
3
Transmit Buffer Empty
THRE
0
Undefined
If more than one category of interrupt is asserted, only the highest priority ID is given.
The line and modem status interrupts are cleared by reading the corresponding status register (LSR (0x001C)).
The receiver buffer full interrupt is cleared when all of the data is read from the receive buffer. The transmitter
buffer empty is cleared when data is written to the TBR register (0x0004).