MEDIATEK Ralink MT7620 - Table of Figures

PGMT7620_V.1.0_040503
Page 8 of 523
MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
Table of Figures
FIGURE 1-1 MT7620 BLOCK DIAGRAM .......................................................................................................................... 2
FIGURE 1-1 MIPS 24KEC PROCESSOR .......................................................................................................................... 12
FIGURE 1-2 MT7620 CLOCK DIAGRAM ........................................................................................................................ 14
FIGURE 1-3 CPU CLOCK MUX ..................................................................................................................................... 15
FIGURE 2-1 SYSTEM CONTROL BLOCK DIAGRAM ............................................................................................................. 17
FIGURE 2-2 TIMER BLOCK DIAGRAM ............................................................................................................................. 47
FIGURE 2-3 INTERRUPT CONTROLLER BLOCK DIAGRAM .................................................................................................... 53
FIGURE 2-4 UART BLOCK DIAGRAM ............................................................................................................................. 62
FIGURE 2-5 UART LITE BLOCK DIAGRAM ...................................................................................................................... 72
FIGURE 2-6 PROGRAMMABLE I/O BLOCK DIAGRAM ........................................................................................................ 81
FIGURE 2-7 I2C CONTROLLER BLOCK DIAGRAM .............................................................................................................. 97
FIGURE 2-8 NORMAL MODE FLOW ............................................................................................................................. 105
FIGURE 2-9 24-BIT ECC GENERATED FROM 512-BYTE DATA .......................................................................................... 106
FIGURE 2-10 HARDWARE ECC DETECTION FLOWCHART ................................................................................................. 107
FIGURE 2-11 PCM CONTROLLER BLOCK DIAGRAM ........................................................................................................ 116
FIGURE 2-12 GENERIC DMA CONTROLLER BLOCK DIAGRAM ........................................................................................... 132
FIGURE 2-13 SPI CONTROLLER BLOCK DIAGRAM .......................................................................................................... 139
FIGURE 2-14 I
2
S TRANSMITTER BLOCK DIAGRAM .......................................................................................................... 152
FIGURE 2-15 I2S TRANSMIT/RECEIVE ......................................................................................................................... 153
FIGURE 2-16 SRAM/SDRAM CONTROLLER BLOCK DIAGRAM ........................................................................................ 159
FIGURE 2-17 QOS ARBITRATION BLOCK DIAGRAM ........................................................................................................ 178
FIGURE 2-18 USB HOST CONTROLLER & PHY BLOCK DIAGRAM ...................................................................................... 183
FIGURE 2-19 USB DEVICE CONTROLLER BLOCK DIAGRAM .............................................................................................. 186
FIGURE 2-20 DE-AGGREGATION FLOW ........................................................................................................................ 188
FIGURE 2-21 BULK-OUT AGGREGATION FORMAT .......................................................................................................... 189
FIGURE 2-22 PDMA TX DESCRIPTOR FORMAT ............................................................................................................. 190
FIGURE 2-23 PDMA RX DESCRIPTOR FORMAT ............................................................................................................. 191
FIGURE 2-24 USB DEVICE REGISTER MAPPING ............................................................................................................. 192
FIGURE 2-25 FRAME ENGINE BLOCK DIAGRAM ............................................................................................................. 203
FIGURE 2-26 PDMA FIFO-LIKE RING CONCEPT ........................................................................................................... 204
FIGURE 2-27 PDMA TX DESCRIPTOR FORMAT ............................................................................................................. 205
FIGURE 2-28 PDMA RX DESCRIPTOR FORMAT ............................................................................................................. 207
FIGURE 2-29 ETHERNET SWITCH BLOCK DIAGRAM ........................................................................................................ 238
FIGURE 2-30 PHY ADDRESS DECODING (I)................................................................................................................... 347
FIGURE 2-31 PHY ADDRESS DECODING (II) .................................................................................................................. 348
FIGURE 2-32 PCIE HOST TOPOLOGY ........................................................................................................................... 354
FIGURE 2-33 PCIE AP MODE .................................................................................................................................... 355
FIGURE 2-34 PCIE CONTROLLER BEHAVING AS A PCIE ENDPOINT ..................................................................................... 356
FIGURE 2-35 PCIE RC/EP BLOCK DIAGRAM ................................................................................................................ 357
FIGURE 2-36 PCIE MEMORY SPACE PROGRAMMABLE MAPPING...................................................................................... 358
FIGURE 2-37 PCI MEMORY SPACE FIXED MAPPING ....................................................................................................... 358
FIGURE 2-38 I/O SPACE PROGRAMMABLE MAPPING ..................................................................................................... 358
FIGURE 2-39 802.11N 2T2R MAC/BBP BLOCK DIAGRAM ........................................................................................... 368
FIGURE 2-40 802.11N 2T2R MAC/BBP REGISTER MAP .............................................................................................. 369
FIGURE 3-1 SECURITY KEY MEMORY LOCATIONS ........................................................................................................... 476
FIGURE 4-1 TXD AND TX FRAME INFORMATION ............................................................................................................ 481
FIGURE 4-2 TXD FORMAT ........................................................................................................................................ 482
FIGURE 4-3 RX DESCRIPTOR RING .............................................................................................................................. 488