MEDIATEK Ralink MT7620 - Register Descriptions ( Base: 0 X 1000_0900)

PGMT7620_V.1.0_040503
Page 99 of 523
MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
2.9.4 Register Descriptions (base: 0x1000_0900)
111. CONFIG: I
2
C Configuration Register (offset: 0x0000)
Bits
Type
Name
Description
Initial Value
31:8
-
-
Reserved
-
7:5
RW
ADDRLEN
Address Length
The value written to this register plus one
indicates the number of address bits to be
transferred from the I2C ADDR register.
0: Transfers a 1-bit address
1: Transfers a 2-bit address, etc.
0x0
4:2
RW
DEVADLEN
Device Address Length
The value written to this register plus one
indicates the number of device address bits to
be transferred from the DEVADDR register. This
field should be programmed to 6 for
compliance with I2C bus protocol.
0x0
1
RW
ADDRDIS
Address Disable
Selects whether the address is included in
transmission.
0: Normal transfers occur with the address
included in the transfer, followed by read or
write data.
1: The controller reads or writes serial data
without transferring the address.
0x0
0
RW
DEVADDIS
Device Address Disable
0: The device address is transmitted before the
data address.
1: The controller does not transfer the device
address.
NOTE:
1. If this bit is set, the ADDRDIS bit is ignored,
and an address is always transmitted.
2. Most I
2
C slave devices require a device
address to be transmitted; this bit should
typically be set to 0.
0x0
112. CLKDIV: I
2
C Clock Divisor Register (offset: 0x0004)
Bits
Type
Name
Description
Initial Value
31:16
-
-
Reserved
0x0