MEDIATEK Ralink MT7620 - Block Diagram; Features; Uart Lite

PGMT7620_V.1.0_040503
Page 72 of 523
MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
2.7 UART Lite
2.7.1 Features
 2-pin UART
 16550-compatible register set, except for Divisor Latch register
 5-8 data bits
 1-2 stop bits (1 or 2 stop bits are supported with 5 data bits)
 Even, odd, stick or no parity
 All standard baud rates up to 345600 b/s
 16-byte receive buffer
 16-byte transmit buffer
 Receive buffer threshold interrupt
 Transmit buffer threshold interrupt
 False start bit detection in asynchronous mode
 Internal diagnostic capabilities
 Break simulation
 Loop-back control for communications link fault isolation
2.7.2 Block Diagram
Baud Rate
Generator
CPU Interface
Interrupts
Transmit FIFO
Receive FIFO
Status Protocol Control
Serializer
Deserializer
TXD
RXD
clock
reset
from System
Controller
CPU Interface
from PalmBus
Controller
Interrupt
to Interrupt
Controller
Figure 2-5 UART Lite Block Diagram