MEDIATEK Ralink MT7620 - Block Diagram

PGMT7620_V.1.0_040503
Page 12 of 523
MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
1.2 Block Diagram
Instruction
scratchpad
RAM
i-cache 0/8/16/32/64 KB
4-way set associative
Trace
TAP
CorExtend
Fetch Unit
8-entry instruction buffer
512-entry BHT
4-entry RPS
Execution Unit
(RF/ALU/
Shift)
BIU
4-entry merging
write buffer,
10 outstanding
reads
MMU
16/32/64 JTLB or FMT
Non-blocking load/store
unit
8 outstanding misses
D-cache
0/8/16/32/64 KB
4-way set associative
Data scratchpad
RAM
System Co-
processor
Power
Managment
CP2
MDU
EJTAG
Off/on chip
trace I/F
Off-chip
Debug I/F
OCP
Interface on-
chip Bus(es)
DSPRAM
DMA OCP
Interface
User-defined
COP2 block
User-defined
CorExtend
block
ISPRAM DMA
OCP I/F
Fixed / Required
Optional
Figure 1-1 MIPS 24KEc Processor