MEDIATEK Ralink MT7620 - Register Descriptions ( Base: 0 X 1000_0 D 00)

PGMT7620_V.1.0_040503
Page 61 of 523
MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
2.5.2 Register Descriptions (base: 0x1000_0d00)
43. STCK_CNT_CFG: MIPS Configuration Register (offset: 0x0000)
Bits
Type
Name
Description
Initial Value
31:2
-
-
Reserved
-
1
RW
EXT_STK_EN
External System Tick Enable
Selects the system tick source
0: Use the MIPS internal timer interrupt.
1: Use the external timer interrupt from an
external MIPS counter.
0x0
0
RW
CNT_EN
Count Enable
Enables the free run counter (MIPS counter).
This counter increments every 20 μs.
0: Disable
1: Enable
0x0
44. CMP_CNT: MIPS Compare Register (offset: 0x0004)
Bits
Type
Name
Description
Initial Value
31:16
-
-
Reserved
-
15:0
RW
CMP_CNT
Compare Count
Sets the cutoff point for the free run counter
(MIPS counter). If the free run counter equals
the compare counter, then the timer circuit
generates an interrupt. The interrupt remains
active until the compare counter is written
again.
0x0
45. CNT: MIPS Counter Register (offset: 0x0008)
Bits
Type
Name
Description
Initial Value
31:16
-
-
Reserved
-
15:0
RW
CNT
MIPS Counter
The MIPS counter (free run counter) increases
by 1 every 20 μs (50 KHz). The counter
continues to count until it reaches the value
loaded into CMP_CNT.
0x0