MEDIATEK Ralink MT7620 - List of Registers

PGMT7620_V.1.0_040503
Page 73 of 523
MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
2.7.3 List of Registers
No.
Offset
Register Name
Description
Page
59
0x0000
RBR
Receive Buffer Register
74
60
0x0004
TBR
Transmit Buffer Register
74
61
0x0008
IER
Interrupt Enable Register
74
62
0x000C
IIR
Interrupt Identification Register
75
63
0x0010
FCR
FIFO Control Register
76
64
0x0014
LCR
Line Control Register
76
65
0x0018
MCR
Modem Control Register
77
66
0x001C
LSR
Line Status Register
78
67
0x0028
DL
Clock Divider Divisor Latch
79
68
0x002C
DLLO
Clock Divider Divisor Latch Low
79
69
0x0030
DLHI
Clock Divider Divisor Latch High
80
70
0x0034
IFCTL
Interface Control
80