MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
2.3 Timer
2.3.1 Features
Independent clock pre-scale for each timer.
Independent interrupts for each timer.
Two general-purpose timers which run at a 40 MHz clock rate. The other two run at a 32 kHz clock rate.
Periodic mode
Free-running mode
Time-out mode
Second timer may be used as a watchdog timer. Watchdog timer resets system on time-out.
Timer Modes
Periodic
In periodic mode, the timer counts down to zero from the load value. An interrupt is generated when the
count is zero. After reaching zero, the load value is reloaded into the timer and the timer counts down
again. A load value of zero disables the timer.
Timeout
In timeout mode, the timer counts down to zero from the load value. An interrupt is generated when the
count is zero. In this mode, the ENABLE bit is reset when the timer reaches zero, stopping the
counter. After reaching zero, the load value is reloaded into the timer. A load value of zero disables the
timer.
Free-running
In free-running mode, the timer counts down to zero from FFFFh. An interrupt is generated when the
count is zero. After reaching zero, FFFFh is reloaded into the timer. This mode is identical to the periodic
mode with a load value of 65535. It is worth noting that if firmware writes to the load value register in
this mode, the timer will still load that value even though that value will be ignored thereafter. Also note
that when the timer is first enabled, it will begin counting down from its current value, not necessarily
FFFFh.
Watchdog
In watchdog mode, the timer counts down to zero from the load value. If the load value is not reloaded or
the timer is not disabled before the count is zero, the chip will be reset. When this occurs, every register
in the chip is reset except the watchdog reset status bit WDRST in the RSTSTAT register in the system
control block; it remains set to alert firmware of the timeout event when it re-executes its bootstrap.
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