MEDIATEK Ralink MT7620 - Ddr Initialization Sequence

PGMT7620_V.1.0_040503
Page 161 of 523
MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
2.15.5 DDR Initialization Sequence
DDR devices require an initialization sequence before they are ready for re-write access.
The initialization sequence is described below.
1. Wait for 200 μs to set bit[10] to 0 in address 0x1000_0034.
2. Read bit[21] of DDR_CFG1 and wait for it to become 1.
3. Set DDR size and data width in DDR_CFG1 (Please refer to the table).
For DDR Performance, follow the settings provided in these two tables for DDR_CFG0 and DDR_CFG1
according to their DDR sizes. The tables are based on a DDR frequency of 193 MHz.
DDR1: DDR_CFG0/1
DDR
SIZE
WIDTH
Total
Width
DDR_CFG0 (tRFC/tREFI)
DDR_CFG1
MT7620N
(DRQFN)
MT7620A
(TFBGA)5
64 Mb
16
16
32’h34A1EB59
32’h20262324
V
V
128 Mb
16
16
32’h34A1EB59
32’h202A2324
V
V
256 Mb
16
16
32’h34A1E5AC
32’h202E2324
V
V
512 Mb
16
16
32’h3421E5AC
32’h20322324
V
V
1 Gb
16
16
32’h241B05AC
32’h20362334
V
DDR2: DDR_CFG0/1
DDR
SIZE
WIDTH
Total
Width
DDR_CFG0 (tRFC/tREFI)
DDR_CFG1
MT7620N
(DRQFN)
MT7620A
(TFBGA)
128 Mb
16
16
32’h2499E5AC
32’h222A2323
V
V
256 Mb
16
16
32’h2519E2D6
32’h222e2323
V
V
512 Mb
16
16
32’h249AA2D6
32’h22322323
V
V
1 Gb
16
16
32’h249B22D6
32’h22362323
V
2 Gb
16
16
32’h249CE2D6
32’h223A2323
V
DDR1: DDR_CFG2: 32’h28000033
DDR2: DDR_CFG2: 32’h68000C43
DDR1: DDR_CFG3: 32’h00000002
DDR2: DDR_CFG3: 32’h00000416
DDR1:DDR_CFG4:32’h00000000
DDR2:DDR_CFG4:32’h0000000A