MEDIATEK Ralink MT7620 - Register Descriptions ( Base: 0 X 1000_0 B00)

PGMT7620_V.1.0_040503
Page 141 of 523
MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
2.13.4 Register Descriptions (base: 0x1000_0B00)
170. SPISTAT0: SPI Interface 0 Status (offset: 0x0000)
Bits
Type
Name
Description
Initial Value
31:1
-
-
Reserved
-
0
RO
BUSY
Indicates SPI transfer in progress
0: The SPI interface is inactive.
1: An SPI transfer is in progress.
NOTE: This bit must be set to 0 before initiating
a transfer. Any attempt to start a data transfer
is ignored if this bit is a 1.
0x0
171. Reserved (offset: 0x0004)
Bits
Type
Name
Description
Initial Value
31:0
-
-
Reserved
0x0
172. Reserved: (offset: 0x0008)
Bits
Type
Name
Description
Initial Value
31:0
-
-
Reserved
0x0
173. Reserved: (offset: 0x000C)
Bits
Type
Name
Description
Initial Value
31:6
-
-
Reserved
0x0
174. SPICFG0: SPI Interface 0 Configuration (offset: 0x0010)
Bits
Type
Name
Description
Initial Value
31:13
-
-
Reserved
-
12
RW
ADDRMODE
SPI Address Mode
0: 3-Byte address mode
(for SPI flash <= 128 Mb)
1: 4-Byte address mode
(for SPI flash >= 256 Mb)
0x0
11
RW
RXENVDIS
Rx Pre-Envelope Disable
Disables setting a pre-data input before the first
data is received.
0: Enable clock PRE_ENVELOP (slave mode)
1: Disable clock PRE_ENVELOP (SPI flash mode)
0x0
10
RW
RXCAP
Rx Capture Delay Mode
0: Rx data capture is not delayed.
1: Rx data capture is delayed for half an SPICLK
cycle
0x0