MEDIATEK Ralink MT7620 - Page 142

PGMT7620_V.1.0_040503
Page 142 of 523
MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
Bits
Type
Name
Description
Initial Value
9
RW
SPIENMODE
SPI Enable Mode
0: SPI Enable is controlled by SW register
settings (SPICTL0)
1: SPI Enable is controlled by HW (SPI Flash
CMD)
0x0
8
RW
MSBFIRST
Bit Transfer Order
0: LSB bits of data sent/received first.
1: MSB bits of data sent/received first.
NOTE: This bit applies to both the command
and data.
0x1
7
-
-
Reserved
-
6
RW
SPICLKPOL
SPI Clock Default Polarity
Sets the default state of the SPICLK
0: Logic 0
1: Logic 1
NOTE: This bit is ignored if the SPI interface
block is a slave (SPISLAVE bit is set).
0x0
5
RW
RXCKEDGE
Rx Clock Capture Edge
0: Data is captured on the rising edge of the
SPICLK signal.
1: Data is captured on the falling edge of the
SPICLK signal.
0x0
4
RW
TXCKEDGE
Tx Clock Transmit Edge
0: Data is transmitted on the rising edge of the
SPICLK signal.
1: Data is transmitted on the falling edge of the
SPICLK signal.
0x0
3
RW
HIZSPI
Tri-state all SPI pins
0: SPICLK and SPIENA pin are driven.
1: SPICLK and SPIENA pin are tri-stated.
NOTE: This bit overrides all normal
functionality.
0x0
2:0
RW
SPICLK
SPI Clock Divide Control
0: SPICLK rate is system clock rate / 2
1: SPICLK rate is system clock rate / 4
2: SPICLK rate is system clock rate / 8
3: SPICLK rate is system clock rate / 16
4: SPICLK rate is system clock rate / 32
5: SPICLK rate is system clock rate / 64
6: SPICLK rate is system clock rate / 128
7: SPICLK is disabled.
NOTE: These rates may change in the future.
0x4
175. SPICTL0: SPI Interface 0 Control (offset: 0x0014)
Bits
Type
Name
Description
Initial Value
31:5
-
-
Reserved
-